1) Field of the Invention
The present invention relates to a lead frame, specifically to a lead frame for flip-chip connection of a semiconductor element in manufacturing a QFN package (Quad Flat Non-leaded Package).
2) Description of Related Art
In recent years, in place of a semiconductor device in which a semiconductor element and substrate terminals are interconnected by wire bonding, there has come to be popular a semiconductor device in which flip-chip connection is established with favorable electric characteristics because of a short wiring resulting from a reduced mounting area.
As a flip-chip connection method, there is, for example, as described in Japanese Patent Application Laid-Open (KOKAI) No. 2013-138261, a method in which a semiconductor element is mounted on substrate terminals in manufacturing of a QFN package via a solder and in which the solder is melted by reflow to thereby establish connection between the semiconductor element and the substrate terminals.
The flip-chip connection method is a mount technique suitable for next-generation semiconductor devices that are becoming smaller, thinner, higher in frequency and higher in speed.